Bit line structure for a multilevel, dual-sided nonvolatile memory cell array

ABSTRACT

A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columnar bit line structure such that each column of the dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells.

This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application Ser. No. 60/903,731, filed on Feb. 26, 2007, which is herein incorporated by reference in its entirety.

This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application Ser. No. 60/904,294, filed on Feb. 28, 2007, which is herein incorporated by reference in its entirety.

This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application Ser. No. 60/918,116, filed on Mar. 14, 2007, which is herein incorporated by reference in its entirety.

RELATED PATENT APPLICATIONS

Attorney's Docket AP07-001, U.S. patent application Ser. No. application Ser. No. ______ filed on ______, assigned to the same assignee as the present invention, and incorporated herein by reference in its entirety.

Attorney's Docket AP07-003, U.S. patent application Ser. No. ______ filed on ______, assigned to the same assignee as the present invention, and incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to nonvolatile memory array structure and operation. More particularly, this invention relates to bit line structure of dual-sided charge-trapping nonvolatile memory cells. Even more particularly, this invention relates to array bit line structure of multilevel dual-sided charge-trapping nonvolatile memory cell for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of the dual-sided charge-trapping nonvolatile memory cells.

2. Description of Related Art

Nonvolatile memory is well known in the art. The different types of nonvolatile memory include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the Flash Memory has become one of the more popular types of Nonvolatile Memory. Flash Memory has the combined advantages of the high density, small silicon area, low cost and can be repeatedly programmed and erased with a single low-voltage power supply voltage source.

The Flash Memory structures known in the art employ a charge storage mechanism and a charge trapping mechanism. The charge storage regime, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell determine that digital data stored. In a charge trapping regime, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiN_(x)). The trapping structure of the charge trapping layer is such that it is possible to store two bits of data in a single SONOS/MONOS nonvolatile memory cell.

U.S. Pat. No. 5,768,192 (Eitan) illustrates a charge trapping non-volatile semiconductor memory cell utilizing asymmetrical charge trapping. The programmable read only memory (PROM) has a trapping dielectric sandwiched between two silicon dioxide layers The trapping dielectric are silicon oxide-silicon nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charge trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting control gate layer is placed over the upper silicon dioxide layer. The memory device is programmed using hot hole programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot holes are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device is read in the opposite direction from which it was written. The reading voltages are applied to the gate and the source while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region.

U.S. Pat. No. 7,187,030 (Chae, et al.) describes a SONOS memory device, and a method for erasing data from the SONOS memory device. The erasing includes injecting charge carriers of a second sign into a trapping film, which has trapped charge carriers of a first sign to store data in the trapping film. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes.

U.S. Pat. No. 7,170,785 (Yeh) illustrates a method and apparatus for operating a string of charge trapping memory cells. The string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

U.S. Pat. No. 7,158,411 (Yeh, et al.) provides a memory architecture for an integrated circuit that includes a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays are formed of charge storage based nonvolatile memory cells.

U.S. Pat. No. 7,151,293 (Shiraiwa, et al.) describes SONOS memory with inversion bit-lines. The SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

U.S. Pat. No. 7,120,063 (Liu, et al.) illustrates flash memory cells that include a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

The nonvolatile memory cells of the prior art are often configured as NAND cell structures. U.S. Pat. No. 6,614,070 and U.S. Pat. No. 6,163,048 (Hirose, et al.) describe a semiconductor nonvolatile memory device having a NAND cell structure. A NAND stack of nonvolatile memory cell transistors is placed within a well formed on a semiconductor substrate. The series nonvolatile memory cell transistors have threshold voltages that are electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

“A 146-mm² 8-Gb Multi-Level NAND Flash Memory with 70-nm CMOS Technology”, Hara, et al., IEEE Journal of Solid-State Circuits, January 2006, Vol.: 41, Issue: 1, pp.: 161-169 provides an 8-Gb multi-level NAND Flash memory with 4-level programmed cells.

“NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, Eitan, et al., IEEE Electron Device Letters, November 2000, Vol.: 21, Issue: 11, pp.: 543-545, presents a novel flash memory cell based on localized charge trapping in a dielectric layer. It is based on the storage of a nominal ˜400 electrons above a n+/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The read methodology is sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability.

“A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes”, Cho et al. IEEE Journal of Solid-State Circuits, November 2001, Vol.: 36, Issue: 11, pp.: 1700-1706, describes a 116.7-mm² NAND flash memory having two modes: a 1-Gb multilevel program mode (MLC) and a high-performance 512-Mb single-level program cell (SLC) modes. A two-step bit line setup scheme suppresses the peak current below 60 mA. A word line ramping technique avoids program disturbance. The SLC mode uses the 0.5-V incremental step pulse and self-boosting program inhibit scheme to achieve high program performance, and the MLC mode uses 0.15-V incremental step pulse and local self-boosting program inhibit scheme to tightly control the cell threshold voltage Vth distributions.

U.S. Pat. No. 7,203,092 (Nazarian) provides a memory array having rows and columns of flash memory cells. Each column of the memory cells is arranged as NAND series strings of memory cells. Each NAND series string having a top select transistor and a bottom select transistor. The top select transistor and the bottom select transistor are coupled to bit lines, such that alternate bit lines are operated either as source lines or bit lines in response to bit line selection and biasing.

The structure of a multiple bit programming of nonvolatile memory cells is known in the art as described in “Intel StrataFlash™ Memory Technology Overview”, Atwood, et al., Intel Technology Journal, Vol. 1, Issue 2, Q4 1997, found www.intel.com, Apr. 23, 2007. The nonvolatile memory cells include a single transistor with an isolated floating gate. The flash cell is an analog storage device in that it stores charge (quantized at a single electron) not bits. By using a controlled programming technique, it is possible to place a precise amount of charge on the floating gate. The charge can be accurately placed to one of four charge states (or ranges) that describe two bits. Each of the four charge states is associated with a two-bit data pattern. The number of states required is equal to 2N where N is the desired number of bits. Threshold of the flash cells is then determined to read the digital data stored in the flash cell.

U.S. Pat. No. 7,113,431 (Hamilton, et al.) pertains to a technique for erasing bits in a dual bit memory in a manner that maintains complementary bit disturb control of bit-pairs of memory cells wherein each bit of the dual bit memory cell can be programmed to multiple levels. One exemplary method comprises providing a word of memory cells after an initial erasure and programming of the bits of the word to one or more of the higher program levels. A disturb level is determined for each of the bit-pairs of the word. A combined disturb level is then computed that is representative of the individual disturb levels. A pattern of drain voltages is then applied to the word for a number of program passes until a target pattern is stored in the word of memory cells based on the combined disturb level and the unprogrammed bit of the bit-pairs is erased to a single program level. This compensates for the disturbance level that exists between the complementary bit-pairs of the word, improves the threshold voltage (Vt) distribution at the program level of the erased state and thereby improves the accuracy of subsequent higher level programming operations and mitigates false or erroneous reads of the states of such program levels.

SUMMARY OF THE INVENTION

An object of this invention is to provide a cross connective columnar bit line structure for an array of multilevel programmed dual-sided nonvolatile memory cells.

Another object of this invention is to provide circuits and methods for the operation of an array of multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure.

To accomplish at least one of these objects, a nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column are formed into at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines. A source/drain of the top select transistor is connected to a first of the associated pair of bit lines. A source/drain of the bottom select transistor is connected to a second of the associated pair of bit lines. The first of the associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells. A source/drain of the top select transistor of the first adjacent column is connected to the second of the associated pair of bit lines and a source/drain of the bottom select transistor of the second adjacent column is connected to the first of the associated pair of bit lines.

A bit line controller is connected to the plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

The nonvolatile memory array further includes a plurality of word lines, a plurality of top select lines, and a plurality of bottom select lines. Each word line is associated with one row of the plurality of dual-sided charge-trapping nonvolatile memory cells. Each top select line connected to a gate of the top select transistor of at least one of the NAND series strings of dual-sided charge-trapping nonvolatile memory cells. Each bottom select line is connected to a gate of the bottom select transistor of at least one of the NAND series strings of dual-sided charge-trapping nonvolatile memory cells. A word line controller is connected to the word lines, the top select lines, and the bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing the trapped charges representing the multiple digital data bits within the charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

The bit line controller has a first bit line program voltage source and a second bit line program voltage source. The first bit line program voltage source provides one of a plurality of threshold adjustment voltages representing a portion of the multiple digital data bits through the first of the associated pair of bit lines to the source/drain of the top select transistor to a first drain/source of the selected dual-sided charge-trapping nonvolatile memory cells to set a first level of the hot carrier charge representing the portion of the multiple digital data bits to charge trapping region. The second bit line program voltage source provides a second of the plurality of threshold adjustment voltages representing another portion of the multiple digital data bits to a second drain/source of the selected dual-sided charge-trapping nonvolatile memory cells to set a second level of the hot carrier charge representing the portion of the multiple digital data bits to charge trapping region.

The word line controller has a word line program voltage source that provides a negative medium large program voltage along with a moderate positive source or drain voltage for generating a voltage field between a control gate of the selected dual-sided charge-trapping nonvolatile memory cells and drain and source regions of the selected dual-sided charge-trapping nonvolatile memory cell to generate hot carriers from the drain and source regions to be injected into a charge trapping region of the selected dual-sided charge-trapping nonvolatile memory cell. The word line controller further includes a first select line program voltage source and a second select line program voltage source. The first select line program voltage source selectively provides a moderately large select voltage to be transferred on the top select lines to activate the top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. The second select line program voltage source selectively provides the moderately large select voltage to be transferred on the bottom select lines to activate the bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells.

The word line controller further has a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of the selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of the plurality of threshold adjustment voltages representative of the portion of multiple digital data bits. The bit line controller also includes a read drain voltage generator that generates a drain voltage level that is selectively transferred through the first and second of the paired bit lines to the first drain/source and the second drain/source to activate the selected dual-sided charge-trapping nonvolatile memory cells dependent upon a trapped charge level within the charge trapping region. A first ground reference voltage generator within the bit line controller generates a ground reference voltage transferred selectively transferred through the first and second of the paired bit lines to the first and second drain/sources. A sensing circuit is connected through the pairs of bit lines to the selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of the charge trapping region representing the multiple digital data bits through the first and second of the paired bit lines.

The word line controller further has a word line erase voltage source that provides a very large erase voltage for generating a voltage field between the channel region of the dual-sided charge-trapping nonvolatile memory cell and the control gate of the dual-sided charge-trapping nonvolatile memory cell. The voltage field from the very large erase voltage injects hot carriers from the channel region into the charge trapping region of the dual-sided charge-trapping nonvolatile memory cell using Fowler-Nordheim tunneling. And the bit line controller also has a second ground reference voltage generator to apply the ground reference voltage to the first and second drain/sources.

In instances where the dual-sided charge-trapping nonvolatile memory cells are n-channel memory cells, the very large program voltage has a level of from approximately −6.0V to approximately −10.0V to cause the hot carrier injection to be a hot hole injection to the charge trapping layer. The plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine the first and second portion of the plurality of the multiple digital data bits. The plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate the plurality of programmed threshold voltages. The drain voltage level must be a voltage level sufficient to overcome threshold voltages of the first and second charge trapping regions and not sufficient to cause soft writing of the dual-sided charge-trapping nonvolatile memory cell. Further, in instances where the dual-sided charge-trapping nonvolatile memory cells are n-channel memory cells, the very large erase voltage has voltage level of from approximately +15.0V to approximately +20V. The very large erase voltage causes injection of hot electrons from the channel region into the charge trapping region of the dual-sided charge-trapping nonvolatile memory cell using Fowler-Nordheim tunneling to increase the threshold voltage of the dual-sided charge-trapping nonvolatile memory cell.

In instances where the dual-sided charge-trapping nonvolatile memory cells are p-channel memory cells, the very large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause the hot carrier injection to be a hot hole injection to the charge trapping layer. The plurality of threshold adjustment voltages have a voltage range of from approximately −1.0V to approximately −6.0V divided into intervals sufficient to determine the first and second portion of the plurality of the multiple digital data bits. The plurality of threshold detection voltages have a voltage range from approximately −2.0V to approximately −5.0V and are divided into increments that differentiate the plurality of programmed threshold voltages. The drain voltage level must be a voltage level sufficient to overcome threshold voltages of the first and second drain sources and not sufficient to cause soft writing of the dual-sided charge-trapping nonvolatile memory cell. Further, in instances where the dual-sided charge-trapping nonvolatile memory cells are a p-channel memory cells, the very large erase voltage has voltage level of from approximately −15.0V to approximately −20V. The very large erase voltage injects hot holes from the channel region into the charge trapping region of the dual-sided charge-trapping nonvolatile memory cell using Fowler-Nordheim tunneling to decrease the threshold voltage of the dual-sided charge-trapping nonvolatile memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a and 1 b are respectively a schematic symbol for and a cross sectional view of a dual-sided charge-trapping nonvolatile memory cell.

FIG. 1 c is a plot of the threshold voltage (V_(t)) for programming each memory cell of an array of dual-sided charge-trapping nonvolatile memory cells versus the number of dual-sided charge-trapping nonvolatile memory cells having a specific threshold voltage for a multiple bit programming by a programming circuit of the control apparatus of this invention.

FIGS. 2 a and 2 b are schematic diagrams of a first and second embodiment of an array of multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure of this invention.

FIG. 3 is a schematic diagram of a general configuration of an array with single NAND Series strings of the multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure for each column of this invention.

FIG. 4 is a block diagram of a general configuration of an array with multiple NAND Series strings of the multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure for each column of this invention.

FIG. 5 is a schematic diagram of a word line controller of the array multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure of this invention.

FIG. 6 is a schematic diagram of a bit line controller of the array of multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure of this invention.

FIGS. 7 a, 7 b, and 7 c are tables of the voltages respectively necessary for programming, erasing, and reading the array of multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure of this invention.

FIG. 8 is a process diagram for the formation of an multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure of this invention.

FIGS. 9 a and 9 b are portions respectively of the array of multilevel programmed dual-sided nonvolatile memory cells with a cross connective columnar bit line structure of this invention of FIGS. 2 a and 2 b for illustrating the programming and reading of the selected multilevel programmed dual-sided nonvolatile memory cells.

DETAILED DESCRIPTION OF THE INVENTION

A nonvolatile memory array of this invention is formed of dual-sided charge-trapping nonvolatile memory cells that are arranged in rows and columns. Groupings of dual-sided charge-trapping nonvolatile memory cells on each column are arranged in a NAND series strings. Each NAND series string has a top select transistor and a bottom select transistor connected in series with each of the groupings of the dual-sided charge-trapping nonvolatile memory cells. Each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines. A source/drain of the top select transistor is connected to a first of the associated pair of bit lines and a source/drain of the bottom select transistor is connected to a second of the associated pair of bit lines.

The first of the associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is also associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells. A source/drain of the top select transistor of the groupings of the dual-sided charge-trapping nonvolatile memory cells of the first adjacent column are connected to the second of the associated pair of bit lines and a source/drain of the bottom select transistor of groupings of the dual-sided charge-trapping nonvolatile memory cells of the second adjacent column are connected to the first of the associated pair of bit lines.

A bit line controller is connected to the plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

The control gate of each of the dual-sided charge-trapping nonvolatile memory cells on each row of the nonvolatile memory array of this invention is connected to a word line. Each gate of the top select transistor of the NAND series groupings of the dual-sided charge-trapping nonvolatile memory cells is connected to a top select line. Similarly, each gate of the bottom select transistors of the NAND series grouping of the dual-sided charge-trapping nonvolatile memory cells is connected to a bottom select line. A word line controller is connected to the word lines, the top select lines, and the bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing the trapped charges representing the multiple digital data bits within the charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

Refer now to FIGS. 1 a and 1 b for a discussion Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) dual-sided flash memory cell structure in FIG. 1 a and the schematic symbol in FIG. 1 b for the nonvolatile memory array of this invention. The dual-sided charge-trapping nonvolatile memory cell 5 is formed within a substrate 10. A drain region 15 and source region 20 are formed within the substrate 10. A relatively thin gate oxide or tunneling oxide 30 is deposited on the substrate 10. A charge trapping layer 35 is then formed over the oxide layer 30 above the channel region 25 between drain region 15 and source region 20. A second dielectric oxide layer 40 is placed on top of charge trapping layer 35 to separate the charge trapping layer 35 from a poly-crystalline silicon layer 45. The poly-crystalline silicon layer 45 forms the control gate of the dual-sided charge-trapping nonvolatile memory cell 5. The control gate 45 of the dual-sided charge-trapping nonvolatile memory cell 5, when placed in an array of dual-sided charge-trapping nonvolatile memory cells 5, is connected to a word line terminal 50. The drain 15 is connected to a first bit line terminal 55 and the source 20 is connected to a second bit line terminal 55. The dual-sided flash memory cell stores the digital data bits as trapped charge within the charge trapping layer 35 above the channel 25 that is formed between drain 15 and source 20.

The operation of the multilevel dual-sided flash memory cell 5 consists of an erase operation, a program operation, and a read operation. In the erase operation, the word line terminal 50 is set to a very large erasing voltage that is applied to the control gate 45 to inject the electrons into the trapped charges 65 and 70 from the channel region between drain region 15 and source region 20. The first and second bit line terminals 55 and 60 and thus the drain 15 and source 20 are set to ground reference level. The program operation of the multilevel dual-sided flash memory cell 5 begins by setting the word line terminal 50 to a medium large programming voltage that is applied to the control gate 45. The medium large programming voltage has an opposite polarity of the very large erasing voltage. For programming the charge trapping region 65 nearest the drain region 15, the first bit line terminal 55 and thus the drain 15 is set to the bit line voltage level and the second bit line terminal 60 and thus the source 20 is set to the ground reference voltage. For programming the charge trapping region 70 nearest the source region 20, the second bit line terminal 60 and thus the source 20 is set to the bit line voltage level and the first bit line terminal 55 and thus the drain 15 is set to the ground reference voltage. The read operation begins by setting the word line terminal 50 and thus the control gate 45 to a read voltage level. To read the program state of the charge trapping region 65, the first bit line terminal 55 and thus the drain region 15 is set to the ground reference voltage and the second bit line terminal 60 and thus the source region 20 is set to the drain read voltage level. The threshold voltage (V_(t)) as adjusted by the charge level of the charge trapping region 65 determines the digital data stored in the charge trapping region 65. To read the program state of the charge trapping region 70, the first bit line terminal 55 and thus the drain region 15 is set to the drain read voltage level and the second bit line terminal 60 and thus the source region 20 is set to the ground reference voltage. The threshold voltage (V_(t)) as adjusted by the charge level of the charge trapping region 70 determines the digital data stored in the charge trapping region 70.

The method of operation of this invention for a SONOS/MONOS dual-sided flash memory cell provides multiple bits being stored in each of the charge trapping regions 65 and 70 of FIG. 1 a. In FIG. 1 c, each of the charge trapping regions may have one of four levels 100, 110, 120, and 130 and thus represent two binary bits of the digital data. The threshold voltage level 130 being the erased voltage level as well as the voltage level for the digital data for a digital 11. An array of the SONOS/MONOS dual-sided flash memory cells will be programmed sufficiently long such that the distribution of the threshold voltages (V_(t)) 102, 112, 122, and 132 allow the setting of the word line voltage and thus the control gates of the array to the program voltages VPV1 105, VPV2 115, and VPV3 125. During a read operation the control gate is set at each voltage level to determine the threshold voltage V_(t) representing the two bits of the digital data stored in each of the charge trapping layers.

The nonvolatile memory array 200 of this invention is formed of dual-sided charge-trapping nonvolatile memory cells of FIG. 1 a that are arranged in rows and columns, as illustrated in FIG. 2 a. Groupings 210 a, 210 b, . . . 210 n−1, 210 n, of the dual-sided charge-trapping nonvolatile memory cells 205 resident on each column of the nonvolatile memory array 200 of this invention are connected to form NAND series strings of the dual-sided charge-trapping nonvolatile memory cells 205. Each of the NAND series string groupings 210 a, 210 b, . . . 210 n−1, 210 n have a top select transistor 215 a, 215 b, . . . 215 n−1, 215 n and a bottom select transistor 220 a, 220 b, . . . 220 n−1, 220 n. Each top select transistor 215 a, 215 b, . . . 215 n−1, 215 n has a first source/drain connected to the drain of the top dual-sided charge-trapping nonvolatile memory cell 205 of each of the NAND series string groupings 210 a, 210 b, . . . 210 n−1. Each bottom select transistor 220 a, 220 b, . . . 220 n−1, 220 n has a first source/drain connected to the source of the bottom dual-sided charge-trapping nonvolatile memory cell 205 of each of the NAND series string groupings 210 a, 210 b, . . . 210 n−1, 210 n. The sources and drains of the top select transistors 215 a, 215 b, . . . 215 n−1, 215 n and the bottom select transistor 220 a, 220 b, . . . 220 n−1, 220 n are interchangeable in function and therefore are designated first and second source/drains for clarity.

A second source/drain of the top select transistors 215 a, 215 b, . . . 215 n−1, 215 n are connected to a first of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n. A second source/drain of the bottom select transistor 220 a, 220 b, . . . 220 n−1, 220 n are connected to a second of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n.

Each column (in this embodiment, one of the NAND series string groupings 210 a, 210 b, . . . 210 n−1, 210 n) of the nonvolatile memory array 200 of this invention is associated with a pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n. One of each of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n is further associated with a first adjacent column 210 a, 210 b, . . . 210 n−1, 210 n of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n is further associated with a second adjacent column 210 a, 210 b, . . . 210 n−1, 210 n of the dual-sided charge-trapping nonvolatile memory cells. A second source/drain of the top select transistor of the first adjacent column 210 a, 210 b, . . . 210 n−1, 210 n is connected to the second of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n and a source/drain of the bottom select transistor of the second adjacent column is connected to the first of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n. Having the top select transistor of a one column 210 a, 210 b, . . . 210 n−1, 210 n and the bottom select transistor of an adjacent column 210 a, 210 b, . . . 210 n−1, 210 n connected to one of the bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n provides the cross connective columnar bit line structure of this invention.

All of the bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n are connected to the bit line controller 230. The bit line controller 230 provides the necessary bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells 205 for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

A control gate of each of the dual-sided charge-trapping nonvolatile memory cells 205 on each row of the nonvolatile memory array 200 of this invention is connected to one word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m. The gates of the top select transistors 215 a, 215 b, . . . 215 n−1, 215 n are connected to the top select gate lines 240 a and 240 b. In this embodiment of the nonvolatile memory array 200 of this invention, half of the top select transistors 215 a, 215 b, . . . 215 n−1, 215 n are connected to one of the top select gate lines 240 a and 240 b and the other half are connected to the other of the top select gate lines 240 a and 240 b. The gates of the bottom select transistors 220 a, 220 b, . . . 220 n−1, 220 n are connected to the bottom select gate line 245. All of the one word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m, top select gate lines 240 a and 240 b, and the bottom select gate line 245 are connected to a word line controller 250. The word line controller 250 transfers word line operational voltages for selecting, programming, reading, and erasing the trapped charges representing the multiple digital data bits within the charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells 205.

A second embodiment of the nonvolatile memory array 200 of this invention as formed with dual-sided charge-trapping nonvolatile memory cells of FIG. 1 a is shown in FIG. 2 b. The structure and function of this embodiment is identical to that of FIG. 2 a except the gates of the bottom select transistors 220 a, 220 b, . . . 220 n−1, 220 n. The bottom select transistors 220 a, 220 b, . . . 220 n−1, 220 n are alternately connected to one of the two bottom select gate lines 245 a and 245 b. The activation of the one of the two bottom select gate lines 245 a and 245 b permits alternating columns of the NAND series string groupings 210 a, 210 b, . . . 210 n−1, 210 n to be connected to the bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n, while isolating the alternating columns of the NAND series string groupings 210 a, 210 b, . . . 210 n−1, 210 n which have the gates of the bottom select transistors 220 a, 220 b, . . . 220 n−1, 220 n connected to deactivated of the two bottom select gate lines 245 a and 245 b.

A more generalized structure of the nonvolatile memory array 300 of this invention is formed of dual-sided charge-trapping nonvolatile memory cells of FIG. 1 a that are arranged in rows and columns is illustrated in FIG. 3. Groupings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z, of the dual-sided charge-trapping nonvolatile memory cells 305 resident on each column of the nonvolatile memory array 300 of this invention are connected, as described above, to form NAND series strings of the dual-sided charge-trapping nonvolatile memory cells 305. Each of the NAND series string groupings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z have a top select transistor 315 a, 315 b, 315 c, 315 d, . . . , 315 i, 315 j, 315 k, 315 l, . . . , 315 w, 315 x, 315 y, 315 z and a bottom select transistor 320 a, 320 b, 320 c, 320 d, . . . , 320 i, 320 j, 320 k, 320 l, . . . , 320 w, 320 x, 320 y, 320 z. Each top select transistor 315 a, 315 b, 315 c, 315 d, . . . , 315 i, 315 j, 315 k, 315 l, . . . , 315 w, 315 x, 315 y, 315 z has a first source/drain connected to the drain of the top dual-sided charge-trapping nonvolatile memory cell 305 of each of the NAND series string groupings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z. Each bottom select transistor 320 a, 320 b, 320 c, 320 d, . . . , 320 i, 320 j, 320 k, 320 l, . . . , 320 w, 320 x, 320 y, 320 z has a first source/drain connected to the source of the bottom dual-sided charge-trapping nonvolatile memory cell 305 of each of the NAND series string groupings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z. The sources and drains of the top select transistors 315 a, 315 b, 315 c, 315 d, . . . , 315 i, 315 j, 315 k, 315 l, . . . , 315 w, 315 x, 315 y, 315 z and the bottom select transistor 320 a, 320 b, 320 c, 320 d, . . . , 320 i, 320 j, 320 k, 320 l, . . . , 320 w, 320 x, 320 y, 320 z are interchangeable in function and therefore are designated first and second source/drains for clarity.

A second source/drain of the top select transistors 315 a, 315 b, 315 c, 315 d, . . . , 315 i, 315 j, 315 k, 315 l, . . . , 315 w, 315 x, 315 y, 315 z are connected to a first of the associated pair of bit lines 325 a, 325 b, 325 c, 325 d. A second source/drain of the bottom select transistor 320 a, 320 b, 320 c, 320 d, . . . , 320 i, 320 j, 320 k, 320 l, . . . , 320 w, 320 x, 320 y, 320 z are connected to a second of the associated pair of bit lines 325 a, 325 b, 325 c, 325 d. The second source/drain of the top select transistors 315 a, 315 b, 315 c, and 315 d are connected to the bit line 325 a. The second source/drain of the top select transistors 315 i, 315 j, 315 k, and 315 l are connected to the 325 b. The second source/drain of the top select transistors 315 w, 315 x, 315 y, 315 z is connected to the bit line 325 c.

The second source/drain of the bottom select transistors 320 a, 320 b, 320 c, and 320 d are connected to the bit line 325 b. The second source/drain of the bottom select transistors 320 i, 320 j, 320 k, and 320 l are connected to the 325 c. The second source/drain of the bottom select transistors 320 w, 320 x, 320 y, 320 z are connected to the bit line 325 d.

Each column (in this embodiment, one of the NAND series string groupings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z) of the nonvolatile memory array 300 of this invention is associated with a pair of bit lines 325 a, 325 b, 325 c, 325 d. In this example, multiple groupings of the NAND series strings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z are associated with a single pair of bit lines 325 a, 325 b, 325 c, 325 d. As shown, the NAND series strings 310 a, 310 b, 310 c, and 310 d are associated with the bit lines 325 a and 325 b. The NAND series strings 310 i, 310 j, 310 k, and 310 l are associated with the bit lines 325 b and 325 c. The NAND series strings 310 w, 310 x, 310 y, and 310 z are associated with the bit lines 325 c and 325 d.

It is apparent that one of each of the associated pair of bit lines 325 a, 325 b, 325 c, 325 d is further associated with two adjacent sets of column 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z of dual-sided charge-trapping nonvolatile memory cells. For instance, the bit lines 325 b and 325 c are associated primarily with the columns with the NAND series strings 310 i, 310 j, 310 k, and 310 l, but the bit line 325 b is also associated with the adjacent columns with the NAND series strings 310 a, 310 b, 310 c, 310 d and the bit line 325 c is associated with the adjacent columns with the NAND series strings 310 w, 310 x, 310 y, 310 z.

Having the top select transistor of a one grouping of columns of the NAND series strings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z and the bottom select transistor of an adjacent grouping of columns of the NAND series strings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z connected commonly to one of the bit lines 325 a, 325 b, 325 c, 325 d provides the cross connective columnar bit line structure of this invention.

All of the bit lines 325 a, 325 b, 325 c, and 325 d are connected to the bit line controller 330. The bit line controller 330 provides the necessary bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells 305 for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

A control gate of each of the dual-sided charge-trapping nonvolatile memory cells 305 on each row of the nonvolatile memory array 300 of this invention is connected to one word line 335 a, 335 b, . . . 335 j−1, 335 j, 335 j+1, . . . 335 m−1, 335 m. The gates of the top select transistors 315 a, 315 b, 315 c, 315 d, . . . , 315 i, 315 j, 315 k, 315 l, . . . , 315 w, 315 x, 315 y, 315 z are connected to the top select gate lines 340 a, 340 b, 340 k−1, and 340 k. In this embodiment of the nonvolatile memory array 300 of this invention, each of the top select transistors 315 a, 315 b, 315 c, 315 d, . . . , 315 i, 315 j, 315 k, 315 l, . . . , 315 w, 315 x, 315 y, 315 z for each grouping of the NAND series strings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z are connected to one of the top select gate lines 340 a, 340 b, 340 k−1, and 340 k such that the number of top select gate lines 340 a, 340 b, 340 k−1, and 340 k is equal to the number of columns within each grouping of the NAND series strings 310 a, 310 b, 310 c, 310 d, . . . , 310 i, 310 j, 310 k, 310 l, . . . , 310 w, 310 x, 310 y, 310 z. The gates of the bottom select transistor 320 a, 320 b, 320 c, 320 d, . . . , 320 i, 320 j, 320 k, 320 l, . . . , 320 w, 320 x, 320 y, 320 z are connected to the bottom select gate lines 345 a, 345 b, 345 k−1, and 345 k. All of the word lines 335 a, 335 b, . . . 335 j−1, 335 j, 335 j+1, . . . 335 m−1, 335 m, top select gate lines 340 a, 340 b, 340 k−1, and 340 k, and the bottom select gate lines 345 a, 345 b, 345 k−1, and 345 k are connected to a word line controller 350. The word line controller 350 transfers word line operational voltages for selecting, programming, reading, and erasing the trapped charges representing the multiple digital data bits within the charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells 305.

The grouping of the NAND series strings 310 a, 310 b, 310 c, 310 d, the top select transistors 315 a, 315 b, 315 c, 315 d, and the bottom select transistor 320 a, 320 b, 320 c, 320 d form a dual-sided charge-trapping nonvolatile memory block 355. In FIG. 3, each column of the dual-sided charge-trapping nonvolatile memory cells 305 is a single dual-sided charge-trapping nonvolatile memory block 355 between each pair of the bit lines 325 a, 325 b, 325 c, 325 d. Referring now to FIG. 4, all the dual-sided charge-trapping nonvolatile memory block 455 is identical in structure and function to the dual-sided charge-trapping nonvolatile memory block 355 of FIG. 3. In this embodiment, an even more general version of the nonvolatile memory array 400 of this invention is discussed. Multiple dual-sided charge-trapping nonvolatile memory blocks 455 are now placed in rows and columns. Each of the dual-sided charge-trapping nonvolatile memory blocks 455 have a multiple NAND series string groupings with a connected top select transistor and a connected bottom select transistor as described in FIG. 3. The top select transistors are connected to a first of the associated pair of bit lines 425 a, 425 b, 425 n−2, . . . 425 n−1, 425 n. The bottom select transistors are connected to a second of the associated pair of bit lines 425 a, 425 b, 425 n−2, . . . 425 n−1, 425 n.

A control gate of each of the dual-sided charge-trapping nonvolatile memory cells on each row of the nonvolatile memory array 400 of this invention is connected to one of the word lines 435 a, 435 b, . . . 435 m. The gates of the top select transistors are connected to the top select gate lines 440 a, 440 b, . . . 440 m. In this embodiment of the nonvolatile memory array 400 of this invention, each of the top select transistors for each grouping of the NAND series strings of the are connected to one of the top select gate lines 440 a, 440 b, . . . 440 m such that the number of top select gate lines 440 a, 440 b, . . . 440 m is equal to the number of columns within each grouping of the NAND series strings with in the dual-sided charge-trapping nonvolatile memory blocks 455. The gates of the bottom select transistors of the dual-sided charge-trapping nonvolatile memory blocks 455 are connected to the bottom select gate lines 445 a, 445 b, . . . 445 m. All of the word lines 435 a, 435 b, . . . 435 m, top select gate lines 440 a, 440 b, 440 m, and the bottom select gate lines 445 a, 445 b, . . . 445 m are connected to a word line controller 450. The word line controller 450 transfers word line operational voltages for selecting, programming, reading, and erasing the trapped charges representing the multiple digital data bits within the charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells of the nonvolatile memory array 400 of this invention.

Refer now to FIG. 5 for a description of the functional structure of the word line controller 500 of the nonvolatile memory array of this invention. The word line controller 500 receives a program control signal 505, an erase control signal 510, and a read control signal 515. The program control signal 505, the erase control signal 510, and the read control signal 515 provides the necessary activation commands that determine the operational mode of the nonvolatile memory array of this invention. It will be understood by one skilled in the art that the program control signal 505, the erase control signal 510, and the read control signal 515 may in fact be components of a command word structure that is applied to the word line controller 500 to perform the program, erase, and read functions. A control decoder 520 receives the program control signal 505, the erase control signal 510, and the read control signal 515, decodes the program control signal 505, the erase control signal 510, and the read control signal 515 and activates the necessary word line functional operation units for the program, erase, and read functions of the nonvolatile memory array of this invention.

The functional operation units are connected to the control decoder 520 to receive the commands to selectively activate the word line functional units that include a word line program circuit 535, a word line erase circuit 540, and a word line read circuit 545. The program circuit 535 has a word line program voltage source 536 that is connected to a selected word lines 560 a, 560 b, . . . 560 m−1, 560 m to provide a very large program voltage for generating a voltage field between a control gate of the selected dual-sided charge-trapping nonvolatile memory cells and a channel region of the selected dual-sided charge-trapping nonvolatile memory cell. Hot carriers are extracted from the channel region and are injected into a charge trapping region of the selected dual-sided charge-trapping nonvolatile memory cell.

The program circuit 535 has a first select line program voltage source 537 that selectively provides a moderately large select voltage. The moderately large select voltage is to be transferred on one of the selected top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k to activate the top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. A second select line program voltage source 538 that selectively provides the moderately large select voltage to be transferred on the bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k to activate the bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. The program circuit provides a connection 539 to the ground reference voltage source which is applied to non-selected word lines 560 a, 560 b, . . . 560 m−1, 560 m, non-selected top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k, and the non-selected bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k.

The word line erase circuit 540 has a word line erase voltage source 543 that is connected to the selected word lines 560 a, 560 b, . . . 560 m−1, 560 m to provide a very large erase voltage for generating a voltage field between a control gate of the selected dual-sided charge-trapping nonvolatile memory cells and a channel region of the selected dual-sided charge-trapping nonvolatile memory cell. Hot carriers are injected into the charge trapping region from the channel region of the selected dual-sided charge-trapping nonvolatile memory cell using Fowler-Nordheim tunneling. In the instance where the nonvolatile memory cells are n-channel memory cells the injected hot carriers are hot electrons. In the instance where the nonvolatile memory cells are p-channel memory cells the injected hot carriers are hot holes. The erase circuit 540 has a first select line erase voltage source 541 that selectively provides a first high select voltage. The first high select voltage is to be transferred on one of the selected top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k to activate the top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. A second select line erase voltage source 542 that selectively provides the second high select voltage to be transferred on the bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k to activate the bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. The erase circuit 540 provides a connection 544 to the ground reference voltage source which is applied to non-selected word lines 560 a, 560 b, . . . 560 m−1, 560 m, non-selected top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k, and the non-selected bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k.

The word line read circuit 545 has a word line read voltage source 546 that is connected to the selected word lines 560 a, 560 b, . . . 560 m−1, 560 m to provide a read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells that is turned on or not dependent upon the value of the read voltage (V_(READ)). The voltage level of the of the word line read voltage source 546 is incremented to determine the threshold level (V_(t)) of the selected dual-sided charge-trapping nonvolatile memory cells that represent the multiple digital data bits stored within two charge trapping regions of the selected dual-sided charge-trapping nonvolatile memory cells.

The read circuit 545 has a first select line read voltage source 548 that selectively provides a voltage level equivalent to the power supply voltage source V_(DD). The supply voltage source V_(DD) is to be transferred on one of the selected top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k to activate the top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. A second select line read voltage source 551 that selectively provides a voltage level equivalent to the power supply voltage source V_(DD) to be transferred on the bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k to activate the bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells. The read circuit 545 has a read pass voltage source 547 that provides a pass voltage level (V_(PASS)) that is applied to the non-selected word lines 560 a, 560 b, . . . 560 m−1, 560 m to prevent activation of the non-selected word lines 560 a, 560 b, . . . 560 m−1, 560 m. The read circuit 540 provides a connection 544 to the ground reference voltage source which is applied to non-selected top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k and the non-selected bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k.

An address word 525 defining the portion of the nonvolatile memory array of this invention that is to be programmed, erased, or read is received by the word line address decoder 530. The decoded address is transferred from the word line address decoder 530 to the row select circuit 550. The decoded address determines which row of the nonvolatile memory array 200 of this invention is to be activated. The decoded control signal is transferred to the row select circuit 550 which to determines the operational voltages that are to be transferred to the word lines 560 a, 560 b, . . . 560 m−1, 560 m, the top select gate lines 555 a, 555 b, . . . 555 k−1, 555 k and the bottom select lines 565 a, 565 b, . . . 565 k−1, 565 k to provide the voltage levels necessary for programming, erasing, and reading the selected row of the nonvolatile memory array of this invention

Refer now to FIG. 6 for a description of the functional structure of the bit line controller 600 of the nonvolatile memory array of this invention. The bit line controller 600 receives a program control signal 505, an erase control signal 510, and a read control signal 515. The program control signal 505, the erase control signal 510, and the read control signal 515 provides the necessary activation commands that determine the operational mode of the nonvolatile memory array of this invention, as described above. A control decoder 605 receives the program control signal 505, the erase control signal 510, and the read control signal 515, decodes the program control signal 505, the erase control signal 510, and the read control signal 515 and activates the necessary bit line functional operation units for the program, erase, and read functions of the nonvolatile memory array of this invention.

The functional operation units are connected to the control decoder 605 to receive the commands to selectively activate the bit line functional units that include a bit line program circuit 615, an bit line erase circuit 620, and a bit line read circuit 625. The bit line program circuit 615 has a first and second bit line program voltage source 617 and 618 that is connected to a selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m to provide a bit line program voltages (V_(BLn)) necessary for programming each of the charge trapping regions of the dual-sided flash memory cells of the selected row. These levels are set based on the binary digital data to be stored as the trapped charge in the first and second charge trapping regions of the selected dual-sided flash memory cells.

The bit line erase circuit 620 provides a connection 623 to the ground reference voltage source which is applied to selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m. A bit line inhibit voltage source 622 is connected to the non-selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m to provide a bit line inhibit voltage (V_(INH)) to inhibit erasure of non-selected dual-sided charge-trapping nonvolatile memory cells.

The bit line read circuit 625 has a bit line drain voltage source 627 that is connected to the selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m to provide a read drain voltage (V_(DRAIN)) to the source/drains of the selected dual-sided charge-trapping nonvolatile memory cells that is turned on or not dependent upon the value of the word line read voltage. The bit line read circuit 625 provides a connection 628 to the ground reference voltage source which is applied to opposing source/drain of the selected dual-sided charge-trapping nonvolatile memory cells through the selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m.

The address word 525 that defines the selected portion of the nonvolatile memory array of this invention to be programmed, erased, or read is received by the bit line address decoder 610. The decoded address is transferred from the bit line address decoder 610 to the bit line select circuit 630. The decoded address determines which column of the nonvolatile memory array 200 of this invention is to be activated. The decoded control signal is transferred to the bit line select circuit 610 which to determines the operational voltages that are to be transferred to the selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m to provide the voltage levels necessary for programming, erasing, and reading the selected row of the nonvolatile memory array of this invention.

During the read operation, the current generated by the selected dual-sided charge-trapping nonvolatile memory cells is transferred through the associated pairs of selected bit lines 635 a, 635 b, 635 c, . . . 635 m−2, 635 m−1, 635 m to the bit line select circuit and on to the sense amplifier 640. The sense amplifier detects whether the selected dual-sided charge-trapping nonvolatile memory cells are turned on or not dependent upon the incremented voltage level of the read voltage (V_(READ)). From this determination of the trapped charge level of the selected dual-sided charge-trapping nonvolatile memory cells, the multiple digital data bits within two charge trapping regions are determined.

Returning to FIG. 1 a, the level of charge in each charge trapping region 65 and 70 is adjusted such that threshold voltage level (V_(t)) assumes one of a group of threshold levels based on the charge placed in the charge trapping regions. The plot of the distribution of an array of dual-sided charge-trapping nonvolatile memory cells of this invention versus the threshold voltage V_(t) of FIG. 1 c illustrates the threshold voltage levels 105, 115, and 125 for two binary digits stored in each of the charge trapping regions of the dual-sided charge-trapping nonvolatile memory cells. Again, the programming time is adjusted to provide the distribution 102, 112, 122, and 132 of the SONOS/MONOS dual-sided flash memory cells such that the program voltages VPV1 105, VPV2 115, and VPV3 125 and the erase voltage VEV 135 applied sequentially as the word line voltage to the control gates of the dual-sided charge-trapping nonvolatile memory cells detect the programmed state of the dual-sided charge-trapping nonvolatile memory cells.

The threshold voltage (V_(t)) control of either the first or second charge trapping regions 65 and 70 respectively adjoining the drain and source regions 15 and 20 of the dual-sided charge-trapping nonvolatile memory cells is performed under Band-to-Band hole-injection program independently. This is referred as one-side program for the dual-sided charge-trapping nonvolatile memory cells. Due to the crosstalk program disturb effect, the first programmed threshold voltage (V_(t)) of either first charge trapping region 65 adjoining the drain 15 or the second charge trapping region 70 adjoining the source 20 will be lowered while subsequently programming the charge trapping region at the opposite side of the channel region of the dual-sided charge-trapping nonvolatile memory cells.

As an example, the bit line voltage levels applied through the first bit line or the second bit line to the drain or source respectively are set to be VBL4=3.5V, VBL3=4.0V, VBL2=4.5V, and VBL1=5.0V. It should be noted that these are approximate and may vary as needed for a particular application. Further, the example illustrates two bits of binary digital data stored in each of the charge trapping regions 65 and 70. When the voltages as shown are applied to the first bit line or the second bit line and thus to the drain and source for a program time of 150 μS, the change in threshold voltage level ΔVt would not alter if bit line voltage level VBL3 is applied to either drain or source terminal. Similarly, the change in threshold voltage level ΔVt will be approximately 0.7V when the bit line voltage level VBL2 is applied to either drain or source terminal. The change in threshold voltage level ΔVt will be approximately 1.7V if bit line voltage level VBL2 is applied to either drain or source terminal. The change in threshold voltage level ΔVt will be approximately 2.5V if bit line voltage level VBL1 is applied to either drain or source terminal.

Refer back now to FIG. 2 a for a discussion of the control operation of the nonvolatile memory array 200 of this invention for programming, reading, and erasing trapped charges representing multiple digital data bits within the two charge trapping regions selected dual-sided charge-trapping nonvolatile memory cells 205. Each of the dual-sided charge-trapping nonvolatile memory cells 205 of the nonvolatile memory array 200 of this invention are essentially structured as shown in FIG. 1 a. Multiple digital data bits are stored simultaneously in the two separate charge trapping regions of the selected dual-sided charge-trapping nonvolatile memory cells 205.

To program a selected row of the dual-sided charge-trapping nonvolatile memory cells 205, the bit line program circuit 615 of FIG. 6 within the bit line controller 230 activates the first and second bit line program voltage sources 617 and 618 to provide the bit line program voltages (V_(BLn)) necessary for programming each of the charge trapping regions of the dual-sided flash memory cells of the selected row. The word line program circuit 535 of FIG. 5 within the word line controller 250 activates the word line program voltage source 536 that to provide the medium large program voltage for generating a voltage field between a control gate of the selected dual-sided charge-trapping nonvolatile memory cells and a channel region of the selected dual-sided charge-trapping nonvolatile memory cell. The very large program voltage is from approximately −7.0V to approximately −10.0V for n-channel selected dual-sided charge-trapping nonvolatile memory cells 205. Alternately, if the selected dual-sided charge-trapping nonvolatile memory cells 205 are a p-channel device the word line voltage level is from approximately +7.0V to approximately +10.0V. It should be noted that the hot carrier charges in the n-channel dual-sided charge-trapping nonvolatile memory cells 205 are hot-holes and in the p-channel selected dual-sided charge-trapping nonvolatile memory cells 205 are hot-electrons. The program state of the charge trapping regions of the selected dual-sided charge-trapping nonvolatile memory cells 205 being determined by the number of hot-carriers injected into each of the charge trapping regions.

To program the charge of both of the trapping regions simultaneously, the first bit line program voltage source 617 is set to the bit line voltage level (V_(BLN)) that represents the digital data to programmed to the first charge trapping region and the second bit line program voltage source 618 is set to the bit line voltage level (V_(BLN)) that represents the digital data to programmed to the second charge trapping region. For example if there are to be two binary digits programmed to each of the charge trapping regions, the first bit line program voltage source 617 and the second bit line program voltage source 618 are set according to the voltage levels according to Table 1.

TABLE 1 Binary Digit to first Binary Digit to second charge trapping charge trapping region region 65 of FIG. 1 70 of FIG. 1 V_(BLn) Level V_(BLn) Level 00 00 VBL1 VBL1 00 01 VBL1 VBL2 00 10 VBL1 VBL3 00 11 VBL1 VBL4 01 00 VBL2 VBL1 01 01 VBL2 VBL2 01 10 VBL2 VBL3 01 11 VBL2 VBL4 10 00 VBL3 VBL1 10 01 VBL3 VBL2 10 10 VBL3 VBL3 10 11 VBL3 VBL4 11 00 VBL4 VBL1 11 01 VBL4 VBL2 11 10 VBL4 VBL3 11 11 VBL4 VBL4

As noted in Atwood, et al., “The charge storage ability of the flash memory cell is a key to the storage of multiple bits in a single cell. The flash cell is an analog storage device not a digital storage device. It stores charge (quantized at a single electron) not bits.” The bit line controller 230 and the word line controller 250 of this invention places a precise amount of charge in the charge trapping regions such that in the nonvolatile memory array 200 of this invention the distribution of the charges as shown in FIG. 1 c are sufficiently restricted that program states of each of the charge trapping regions are detectable. In one implementation of the nonvolatile memory array 200 of this invention the distribution of the program states is within a narrow range of differences in threshold voltage levels (ΔVt) are set such that there is a detection window of approximately 1.0V. Assuming the ability to differentiate the differences in threshold voltage levels (ΔV_(t)) for each binary digit of the programmed data, any number of bits conceptually may be programmed by the bit line controller 230 and the word line controller 250 of this invention to the charge trapping regions selected dual-sided charge-trapping nonvolatile memory cells 205.

To erase a selected row of the dual-sided charge-trapping nonvolatile memory cells 205, the bit line erase circuit 620 of FIG. 6 within the bit line controller 230 connects the pairs of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n to the ground reference voltage source 623. Any of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n not being erased are connected to the bit line inhibit voltage source 622 to prevent the erasure of the charge trapping regions. The bit line inhibit voltage source 622 is set to an inhibit voltage level of from approximately +7.5V to approximately +10V. To inject the hot carriers injected during the programming of the selected dual-sided charge-trapping nonvolatile memory cells 205, the word line erase circuit 540 is set to provide a word line erase voltage level of from approximately +15V to approximately +20V for the n-channel dual-sided charge-trapping nonvolatile memory cells 205. Alternately, if the dual-sided charge-trapping nonvolatile memory cells 205 are p-channel devices the word line erase voltage level is from approximately −15V to approximately −20V.

A read operation of the nonvolatile memory array 200 of this invention, is where the first charge trapping region is read in one direction and the second charge trapping region is read in the opposite direction. During each directional read operation, the word line read voltage source 546 within the word line read circuit 545 of the word line controller 250 is connected to the selected word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m to provide a read voltage (V_(READ)). For reading the program state of the first charge trapping region, the word line read voltage source 546 is set to the read voltage level (V_(READ)). The bit line read circuit 625 sets the first of the associated pair of bit lines 425 a, 425 b, 425 n2, . . . 425 n−1, 425 n to the ground reference voltage level (0V) and the second associated pair of bit lines 425 a, 425 b, 425 n2, . . . 425 n−1, 425 n the drain read voltage (V_(DRAIN)). As noted above, the read voltage level (V_(READ)) Must be varied incrementally through each of the threshold boundary voltage levels (VPVn) as shown in FIG. 1 c to determine the program state of the first charge trapping regions. For reading the program state of the second charge trapping regions, the word line voltage source 485 is set to the read voltage level (V_(READ)). The bit line read circuit 625 sets the first of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n to the drain read voltage (V_(DRAIN)) and the second of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n to the ground reference voltage level (0V). Again, as noted above, the read voltage level (V_(READ)) must be varied incrementally through each of the threshold boundary voltage levels (VPVn) as shown in FIG. 1 c to determine the program state of the second charge trapping region of the selected row of the dual-sided charge-trapping nonvolatile memory cells 205.

During the read operation, the sense amplifier 640 of FIG. 6 determines whether the selected dual-sided charge-trapping nonvolatile memory cells 205 are conducting or not in each direction. Based on the threshold boundary voltage level (VPVn) and the conduction of the selected dual-sided charge-trapping nonvolatile memory cells 205, the sense amplifier 460 determines the binary digital data programmed in each of the charge trapping regions and transfers the binary digital data to external circuitry through the data input/output bus 645.

As shown above, the bit line controller 515 and the word line controller 505 function in concert for operation of the nonvolatile memory array 200 of this invention. Refer now to FIGS. 2 a and 7 a for a description of a program operation of the array of dual-sided charge-trapping nonvolatile memory cells 205. A selected row of the dual-sided charge-trapping nonvolatile memory cells 205 is connected to the selected word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m, which has the word line program voltage level (V_(PGM)) applied to the selected word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m and thus to the control gates of the selected dual-sided charge-trapping nonvolatile memory cells 205. The non-selected rows of dual-sided charge-trapping trapping nonvolatile memory cells 205 are connected to the remaining word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m of the nonvolatile memory array 200 of this invention. The word line controller sets these non-selected word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m and thus the non-selected dual-sided charge-trapping nonvolatile memory cells 205 to the ground reference voltage level (0).

The bit line controller 230 generates the bit line program voltage levels (V_(BLn)) necessary for programming each of the charge trapping regions of the dual-sided charge-trapping nonvolatile memory cells 205 of the selected row. The bit line program voltage levels (V_(BLn)) are applied to the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n and thus to the sources and drains of the selected dual-sided charge-trapping nonvolatile memory cells 205. These levels are set based on the binary digital data to be stored as the trapped charge in the first and second charge trapping regions of the selected dual-sided charge-trapping nonvolatile memory cells 205. Examples of these levels of the binary digital data are shown in Table 1.

Erasure of the nonvolatile memory array 200 of dual-sided charge-trapping nonvolatile memory cells 205 of this invention is illustrated in FIGS. 2 a and 7 b. The erasure is shown as a row wise erase, where a selected row received a word line erase voltage level (V_(ERS)) from the selected word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m as applied by the word line controller 250. The word line erase voltage level is from approximately +15V to approximately +20V for n-channel dual-sided charge-trapping nonvolatile memory cells 205 to inject hot electrons into the charge trapping region. Alternately, if the dual-sided charge-trapping nonvolatile memory cells 205 are p-channel devices, the word line erase voltage level is from approximately −15V to approximately −20V to inject hot holes into the charge trapping region. The word line controller 250 applies the ground reference voltage level (0V) to the non-selected word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m and thus to the dual-sided charge-trapping nonvolatile memory cells 205 to prevent removal of the trapped charges from the first and second charge trapping regions of the non-selected dual-sided charge-trapping nonvolatile memory cells 205.

The bit line controller 230 applies the ground reference voltage level (0V) to each of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n for a complete erase. In an array configuration, certain cells require that they not be subjected to the erasure operation. In this circumstance, the bit line controller 230 applies an inhibit voltage level (V_(INH)) of from approximately +7.5V to approximately +10V to those associated pair of bit lines 225 a, 225 b, 225 c,. 225 n−2, 225 n−1, 225 n that are sufficiently erased and do not require further erasure.

Refer now to FIGS. 2 a and 7 c for the explanation of the reading of a selected row of the dual-sided charge-trapping nonvolatile memory cells 205. A selected row of the dual-sided charge-trapping nonvolatile memory cells 205 has the word line read voltage level (V_(READ)) applied to the associated word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m and thus to the control gates of the selected dual-sided charge-trapping nonvolatile memory cells 205. The non-selected rows of dual-sided charge-trapping nonvolatile memory cells 205 are connected to the remaining word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m of the array. The word line controller 250 sets these word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m and thus the dual-sided charge-trapping nonvolatile memory cells 205 to a word line read pass voltage level (V_(PASS)). The word line read pass voltage level (V_(PASS)) insures that the non-selected rows of dual-sided charge-trapping nonvolatile memory cells 205 are not activated during the read operation.

To read the first charge trapping region of the selected rows of dual-sided charge-trapping nonvolatile memory cells 205, the bit line controller 230 sets the first of the associated pairs of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n connected to the first charge trapping regions to the ground reference voltage level (0V) and the second of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n connected to the second charge trapping regions to the drain read voltage (V_(DRAIN)). As noted above, the read voltage level (V_(READ)) must be varied incrementally through each of the threshold boundary voltage levels (VPVn) as shown in FIG. 1 c to determine the program state of the first charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells 205. For reading the program state of the second charge trapping region of the selected dual-sided charge-trapping nonvolatile memory cells 205, the bit line controller 230 sets the first of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n connected to the first charge trapping regions to the drain read voltage (V_(DRAIN)) and the second of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n connected to the second charge trapping regions to the ground reference voltage level (0V). Again, as noted above, the read voltage level (V_(READ)) must be varied incrementally through each of the threshold boundary voltage levels (VPVn) as shown in FIG. 1 c to determine the program state of the second charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells 205.

It should be noted that the drain read voltage (V_(DRAIN)) level must be sufficient to overcome threshold voltages of the first and second charge trapping regions and not sufficient to cause soft writing of the dual-sided charge-trapping nonvolatile memory cells 205.

During the read operation, a sense amplifier within the bit line controller 230 determines whether the selected dual-sided charge-trapping nonvolatile memory cells 205 are conducting or not in each direction. Based on the threshold boundary voltage level (VPVn) and the conduction of the selected dual-sided charge-trapping nonvolatile memory cells 205, the sense amplifier determines the binary digital data programmed in each charge trapping regions of the selected dual-sided charge-trapping nonvolatile memory cells 205 and transfers the binary digital data to external circuitry through an data input/output bus.

Refer now to FIG. 8 for an overview of the construction of the nonvolatile memory array of dual-sided charge-trapping nonvolatile memory cells of this invention. Multiple dual-sided charge-trapping nonvolatile memory cells are provided (Box 700) and arranged (Box 705) into rows and columns. Groups of the dual-sided charge-trapping nonvolatile memory cells on each column of the nonvolatile memory array dual-sided charge-trapping nonvolatile memory cells of this invention are formed (Box 710) into NAND series strings of the dual-sided charge-trapping nonvolatile memory cells. A top select transistors is connected (Box 715) to a top dual-sided charge-trapping nonvolatile memory cell of each of the NAND series strings of the dual-sided charge-trapping nonvolatile memory cells. Similarly, a bottom select transistor is connected (Box 715) to the dual-sided charge-trapping nonvolatile memory cell of each of the NAND series strings of the dual-sided charge-trapping nonvolatile memory cells. Each of the columns of the dual-sided charge-trapping nonvolatile memory cells is associated (Box 720) with a pair of bit lines. Each of the pair of associated bit lines may be associated with an adjacent column of the dual-sided charge-trapping nonvolatile memory cells. A source/drain of each of the top select transistors is connected (Box 725) to a first of the associated pair of bit lines and a source/drain of the bottom select transistor is connected (Box 725) to the second of the associated pair of bit lines. A bit line controller is connected (Box 730) to the associated pairs of bit lines for each of the columns of the nonvolatile memory array of this invention. A word line is associated with each row of the dual-sided charge-trapping nonvolatile memory cells. The dual-sided charge-trapping nonvolatile memory cells is then connected (Box 735) to control gates of each of the dual-sided charge-trapping nonvolatile memory cells on the associated row of the dual-sided charge-trapping nonvolatile memory cells. A word line controller is connected (Box 740) to each of the word lines and thus to control gates of the associated dual-sided charge-trapping nonvolatile memory cells.

The connection of the top select transistor of each grouping of the dual-sided charge-trapping nonvolatile memory cells to the first of the associated bit lines and the connection of the bottom transistor to the second of the associated bit lines brings about the cross connective bit lines structure of the nonvolatile memory array of this invention.

FIG. 9 a illustrates a portion of the nonvolatile memory array 200 of this invention as shown in FIG. 2 a. As described in FIG. 2 a, groupings 210 a, 210 b, 210 c, and 210 d of the dual-sided charge-trapping nonvolatile memory cells 205 resident on each column of the nonvolatile memory array 200 of this invention are connected to form NAND series strings of the dual-sided charge-trapping nonvolatile memory cells 205. Each of the NAND series string groupings 210 a, 210 b, 210 c, and 210 d have a top select transistor 215 a, 215 b, and 215 c and a bottom select transistor 220 a, 220 b,and 220 c. Each top select transistor 215 a, 215 b, and 215 c has a first source/drain connected to the drain of the top dual-sided charge-trapping nonvolatile memory cell 205 of each of the NAND series string groupings 210 a, 210 b, 210 c, and 210 d. Each bottom select transistor 220 a, 220 b,and 220 c has a first source/drain connected to the source of the bottom dual-sided charge-trapping nonvolatile memory cell 205 of each of the NAND series string groupings 210 a, 210 b, 210 c, and 210 d. The sources and drains of the top select transistors 215 a, 215 b, and 215 c and the bottom select transistor 220 a, 220 b,and 220 c are interchangeable in function and therefore are designated first and second source/drains for clarity.

A second source/drain of the top select transistors 215 a, 215 b, and 215 c are connected to a first of the associated pair of bit lines 225 a, 225 b, 225 c, and 225 d. A second source/drain of the bottom select transistor 220 a, 220 b,and 220 c are connected to a second of the associated pair of bit lines 225 a, 225 b, 225 c, and 225 d.

Each column (in this embodiment, one of the NAND series string groupings 210 a, 210 b, and 210 c) of the nonvolatile memory array 200 of this invention is associated with a pair of bit lines 225 a, 225 b, 225 c, and 225 d. One of each of the associated pair of bit lines 225 a, 225 b, 225 c, and 225 d is further associated with a first adjacent column 210 a, 210 b, and 210 c of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines 225 a, 225 b, 225 c, and 225 d is further associated with a second adjacent column 210 a, 210 b, and 210 c of the dual-sided charge-trapping nonvolatile memory cells. A second source/drain of the top select transistor of the first adjacent column 210 a, 210 b, and 210 c is connected to the second of the associated pair of bit lines 225 a, 225 b, 225 c, and 225 d and a source/drain of the bottom select transistor of the second adjacent column is connected to the first of the associated pair of bit lines 225 a, 225 b, 225 c, and 225 d. Having the top select transistor 215 a, 215 b, and 215 c of a one column 210 a, 210 b, and 210 c and the bottom select transistor 220 a, 220 b, and 220 c of an adjacent column 210 a, 210 b, and 210 c connected to one of the bit lines 225 a, 225 b, 225 c, and 225 d provides the cross connective columnar bit line structure of this invention.

As an example, the column containing the NAND series string groupings 210 b is associated with the bit lines 225 b and 225 c. The first adjacent NAND series string grouping 210 a is associated with the bit line 225 b and has the second source/drain of its bottom select transistor 220 a connected to the bit line 225 b. The second adjacent NAND series string grouping 210 c is associated with the bit line 225 c and has the second source/drain of its top select transistor 225 c connected to the bit line 225 c.

All of the bit lines 225 a, 225 b, 225 c, and 225 d are connected to the bit line controller 230. The bit line controller 230 provides the necessary bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells 205 for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells.

A control gate of each of the dual-sided charge-trapping nonvolatile memory cells 205 on each row of the nonvolatile memory array 200 of this invention is connected to one word line 235 a, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m. The gates of the top select transistors 215 a, 215 b, and 215 c are connected to the top select gate lines 240 a and 240 b. In this embodiment of the nonvolatile memory array 200 of this invention, half of the top select transistors 215 a, 215 b, and 215 c are connected to one of the top select gate lines 240 a and 240 b and the other half are connected to the other of the top select gate lines 240 a and 240 b. The gates of the bottom select transistor 220 a, 220 b,and 220 c are connected to the bottom select gate line 245. All of the word lines 235 a, . . . 235 j1, 235 j, 235 j+1, . . . 235 m, top select gate lines 240 a and 240 b, and the bottom select gate line 245 are connected to a word line controller 250. The word line controller 250 transfers word line operational voltages for selecting, programming, reading, and erasing the trapped charges representing the multiple digital data bits within the charge trapping region of each of the selected dual-sided charge-trapping nonvolatile memory cells 205.

The NAND series string groupings 210 a, 210 b, and 210 c of the dual-sided charge-trapping nonvolatile memory cells 205 that have shared word lines 235 a, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m are defined as a page. The programming, erasure, and reading may be on a page or half-page basis, as described hereinafter. In the descriptions of the operation as described below, the word line controller 250 will activate the word line WLj 235 j with the appropriate voltage levels for programming, erasing, or reading the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. Simultaneously, the word line controller will apply the appropriate select line voltage levels to the top select lines 240 a and 240 b to activate the top select transistors 215 a, 215 b, and 215 c and the bottom select line to activate the bottom select transistors 220 a, 220 b, and 220 c to connect the NAND series string groupings 210 a, 210 b, and 210 c to the bit lines 225 a, 225 b, 225 c, and 225 d.

Programming of a full page is a sequential programming of the first charge trapping regions 265 a, 265 b, and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c followed by the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c.

The word line controller 250 activates word line program voltage source 536 of FIG. 5 to place the very large program voltage to the word line WLj 235 j. The very large program voltage is thus applied to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. The word line controller 250 activates the first select line program voltage source 537 to place the moderately large select voltage at the gates of the top select transistors 215 a, 215 b, and 215 c to activate the top select transistors 215 a, 215 b, and 215 c to connect the NAND series string groupings 210 a, 210 b, and 210 c to their associated bit lines 225 a, 225 b, and 225 c. Word line controller 250 connects the ground reference voltage source 539 of FIG. 5 to the gates of the bottom select transistors 220 a, 220 b, and 220 c to deactivate the bottom select transistors 220 a, 220 b, and 220 c and prevent the bottoms dual-sided charge-trapping nonvolatile memory cells 205 of the NAND series string groupings 210 a, 210 b, and 210 c to their second associated bit lines 225 b, 225 c, and 225 d. The bit line controller 230 activates the first bit line program voltage source 617 to place the bit line program voltages (V_(BLn)) on each of the bit lines 225 a, 225 b, 225 c, and 225 d. The bit line program voltages (V_(BLn)) is transferred the top select transistors 215 a, 215 b, and 215 c to the first charge trapping regions 265 a, 265 b, and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c.

After the first charge trapping regions 265 a, 265 b, and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c are sufficiently programmed, the word line controller 250 deactivates the lo first select line program voltage source 537 and connects the ground reference voltage 539 of FIG. 5 to the gates of the top select transistors 215 a, 215 b, and 215 c to turn off the top select transistors 215 a, 215 b, and 215 c. The word line controller 250 the activates the second select line program voltage source 538 of FIG. 5 to provide the moderately large select voltage to the gates of the bottom select transistors 220 a, 220 b, and 220 c to turn on the bottom select transistors 220 a, 220 b, and 220 c. Turning on the bottom select transistors 220 a, 220 b, and 220 c connects the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c to the associated bit lines 225 b, 225 c, and 225 d. The bit line controller 230 the activates the second bit line program voltage source 618 of FIG. 6 to place the bit line program voltages (V_(BLn)) on the associated bit lines 225 b, 225 c, and 225 d and thus to the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c.

During the programming, all the word line controller connects the non-selected word lines 235 a, . . . 235 j−1, 235 j+1, . . . , 235 m to the ground reference voltage source 539 of FIG. 5.

The read operation of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c of the array of nonvolatile memory array 200 of this invention is performed on a half-page of the nonvolatile memory array 200 of this invention. The half-page being alternating columns of the NAND series string groupings 210 a, 210 b, and 210 c of the dual-sided charge-trapping nonvolatile memory cells 205. To perform the half-page read, the word line controller 250 activates the first select line read voltage source 548 and the second select line read voltage source 551 to respectively transferred the voltage level of the power supply voltage source V_(DD) to the top select line 240 a and bottom select line 245 and thus to the top select transistors 215 a, and 215 c to connect the first half-page of the nonvolatile memory array 200 to the associated bit lines 225 a and 225 c. The word line controller 250 connects the top select lines 240 b to the ground reference voltage source 539 of FIG. 5 to deactivate the top select transistor 215 b from its associated bit line 225 b. To read the first charge trapping regions 265 a and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c, the bit line controller 230 connects the first alternating bit lines 225 a and 225 c to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the second alternating bit lines 225 b and 225 d. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c and the value of the charge level of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c and thus the value of the multiple digital data bits retained in the first charge trapping regions 265 a and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c.

After the value of the multiple digital data bits is determined, the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c are then read. The bit line controller 230 connects the second alternating bit lines 225 b and 225 d to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit lines 225 a and 225 c. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)) to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c and the value of the charge level in the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c and thus the value of the multiple digital data bits retained in the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c.

To perform the second half-page read, the word line controller 250 activates the first select line read voltage source 548 and the second select line read voltage source 551 to respectively transferred the voltage level of the power supply voltage source V_(DD) to the top select line 240 b and bottom select line 245 b and thus to the top select transistor 215 b and the bottom select transistor 220 b to connect the second half-page of the nonvolatile memory array 200 to the associated bit lines 225 b and 225 c. The word line controller 250 connects the top select lines 240 a and the bottom select line 245 a to the ground reference voltage source 539 of FIG. 5 to deactivate the top select transistors 215 a and 215 c from their associated bit lines 225 a and 225 c and deactivate the bottom select transistors 220 a and 220 c from their associated bit lines 225 b and 225 d. To read the first charge trapping region 265 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b, the bit line controller 230 connects the second alternating bit line 225 c to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit lines 225 b. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 b that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 b to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and the value of the charge level of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and thus the value of the multiple digital data bits retained in the first charge trapping region 265 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b.

After the value of the multiple digital data bits is determined, the second charge trapping region 270 b of the selected dual-sided charge-trapping nonvolatile memory cell 205 b is then read. The bit line controller 230 connects the second alternating bit lines 225 b to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit line 225 c. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 b to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and the value of the charge level in the second charge trapping regions 270 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and thus the value of the multiple digital data bits retained in the second charge trapping regions 270 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b.

FIG. 9 b illustrates a portion of the nonvolatile memory array 200 of this invention as shown in FIG. 2 b. As described in FIG. 2 b, the structure and function of this embodiment is identical to that of FIG. 2 a except the gates of the bottom select transistors 220 a, 220 b and 220 c. The gates of the bottom select transistors 220 a and 220 c are connected to the bottom select gate line 245 a. The gate of the bottom select transistor 220 b is connected to the bottom select gate line 245 b. The activation of the bottom select gate line 245 a permits the columns of the NAND series string groupings 210 a and 210 c to be connected to the bit lines 225 b and 225 d, while isolating the columns of the NAND series string grouping 210 b which has the gate of the bottom select transistor 220 b, connected to the deactivated bottom select gate line z245 b.

As described above, the NAND series string groupings 210 a, 210 b, and 210 c of the dual-sided charge-trapping nonvolatile memory cells 205 that have shared word lines 235 a, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m are defined as a page. The programming, erasure, and reading may be on a page or half-page basis, as described hereinafter. In the descriptions of the operation as described below, the word line controller 250 will activate the word line WLj 235 j with the appropriate voltage levels for programming, erasing, or reading the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. Simultaneously, the word line controller will apply the appropriate select line voltage levels to the top select lines 240 a and 240 b to activate the top select transistors 215 a, 215 b, and 215 c and the bottom select lines 245 a and 24 b to activate the bottom select transistors 220 a, 220 b, and 220 c to connect the NAND series string groupings 210 a, 210 b, and 210 c to the bit lines 225 a, 225 b, 225 c, and 225 d.

Programming of a full page is a sequential programming of the first charge trapping regions 265 a, 265 b, and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c followed by the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. The programming in the structure of FIG. 9 b is identical to that of FIG. 9 a, except both of the bottom select lines 245 a and 24 b are simultaneously activated.

Having multiple bottom select lines 245 a and 24 b permits multiple digital data bits are stored simultaneously in the first charge trapping regions 265 a, 265 b, and 265 c and the second charge trapping regions 270 a, 270 b, and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. The simultaneous storage of the multiple data bits is accomplished in one-half page units.

To program the first half-page unit, the word line controller 250 activates the word line program voltage source 536 of FIG. 5 to place the very large program voltage to the word line WLj 235 j. The very large program voltage is thus applied to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. The word line controller 250 activates the first select line program voltage source 537 to place the moderately large select voltage at the gates of the top select transistors 215 a and 215 c to activate the top select transistors 215 a and 215 c to connect the NAND series string groupings 210 a and 210 c to their associated bit lines 225 a and 225 c. Word line controller 250 connects the ground reference voltage source 539 of FIG. 5 to the top select line 240 b and thus to the gate of the top select transistor 215 b to isolate the NAND series string grouping 210 b from its first associated bit line 225 b.

The word line controller 250 activates the second select line program voltage source 538 to place the moderately large select voltage at the gates of the bottom select transistors 220 a and 220 c to activate the bottom select transistors 220 a and 220 c and to connect the bottom dual-sided charge-trapping nonvolatile memory cells 205 of the NAND series string groupings 210 a and 210 c to their second associated bit lines 225 b and 225 d. Word line controller 250 connects the ground reference voltage source 539 of FIG. 5 to the bottom select line 245 b and thus to the gate of the bottom select transistor 220 b to isolate the NAND series string grouping 210 b from its second associated bit line 225 c.

The bit line controller 230 activates the first bit line program voltage source 617 to place the bit line program voltages (V_(BLn)) on each of the bit lines 225 a, and 225 c. The bit line program voltages (V_(BLn)) is transferred the top select transistors 215 a, and 215 c to the first charge trapping regions 265 a and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c. Simultaneously, the bit line controller 230 activates the second bit line program voltage source 618 of FIG. 6 to place the bit line program voltages (V_(BLn)) on the associated bit lines 225 b and 225 d and thus to the second charge trapping regions 270 a and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c.

To program the second half-page unit, the word line controller 250 maintains the activation of the word line program voltage source 536 of FIG. 5 to place the very large program voltage to the word line WLj 235 j. The very large program voltage is thus applied to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c. The word line controller 250 activates the first select line program voltage source 537 to place the moderately large select voltage on the top select line 240 b and thus to the gates of the top select transistor 215 b to activate the top select transistor 215 b to connect the NAND series string grouping 210 b and 210 c to its associated bit lines 225 b. Word line controller 250 connects the ground reference voltage source 539 of FIG. 5 to the top select line 240 a and thus to the gate of the top select transistors 215 a and 215 c to isolate the NAND series string groupings 210 a and 210 c from their first associated bit lines 225 a and 225 c.

The word line controller 250 activates the second select line program voltage source 538 to place the moderately large select voltage at the gates of the bottom select transistors 220 b to activate the bottom select transistor 220 b and to connect the bottom dual-sided charge-trapping nonvolatile memory cells 205 of the NAND series string groupings 210 b to its second associated bit lines 225 c. Word line controller 250 connects the ground reference voltage source 539 of FIG. 5 to the bottom select line 245 a and thus to the gate of the bottom select transistors 220 a and 245 c to isolate the NAND series string groupings 210 a and 245 c from their second associated bit lines 225 b and 225 d.

The bit line controller 230 activates the first bit line program voltage source 617 to place the bit line program voltages (V_(BLn)) on each of the bit lines 225 b, and 225 d. The bit line program voltages (V_(BLn)) is transferred the top select transistor 215 b to the first charge trapping region 265 b of the selected dual-sided charge-trapping nonvolatile memory cell 205 b. Simultaneously, the bit line controller 230 activates the second bit line program voltage source 618 of FIG. 6 to place the bit line program voltages (V_(BLn)) on the associated bit line 225 c and thus to the second charge trapping region 270 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b.

During the programming, all the word line controller connects the non-selected word lines 235 a, . . . 235 j−1, 235 j+1, . . . , 235 m to the ground reference voltage source 539 of FIG. 5.

The read operation of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c of the array of nonvolatile memory array 200 of this invention is performed on a half-page of the nonvolatile memory array 200 of this invention. To perform the first half-page read, the word line controller 250 activates the first select line read voltage source 548 and the second select line read voltage source 551 to respectively transferred the voltage level of the power supply voltage source V_(DD) to the top select line 240 a and bottom select line 245 a and thus to the top select transistors 215 a, and 215 c to connect the first half-page of the nonvolatile memory array 200 to the associated bit lines 225 a and 225 c. The word line controller 250 connects the top select lines 240 b and the bottom select line 245 b to the ground reference voltage source 539 of FIG. 5 to deactivate the top select transistor 215 b from its associated bit line 225 b and deactivate the bottom select transistor 220 b from its associated bit line 225 c. To read the first charge trapping regions 265 a and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c, the bit line controller 230 connects the second alternating bit lines 225 b and 225 d to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit lines 225 a and 225 c. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c and the value of the charge level of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c and thus the value of the multiple digital data bits retained in the first charge trapping regions 265 a and 265 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c.

After the value of the multiple digital data bits is determined, the second charge trapping regions 270 a and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c are then read. The bit line controller 230 connects the second alternating bit lines 225 b and 225 d to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit lines 225 a and 225 c. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c and the value of the charge level in the second charge trapping regions 270 a and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c and thus the value of the multiple digital data bits retained in the second charge trapping regions 270 a and 270 c of the selected dual-sided charge-trapping nonvolatile memory cells 205 a and 205 c.

To perform the second half-page read, the word line controller 250 activates the first select line read voltage source 548 and the second select line read voltage source 551 to respectively transferred the voltage level of the power supply voltage source V_(DD) to the top select line 240 b and bottom select line 245 b and thus to the top select transistor 215 b and the bottom select transistor 220 b to connect the second half-page of the nonvolatile memory array 200 to the associated bit lines 225 b and 225 c. The word line controller 250 connects the top select lines 240 a and the bottom select line 245 a to the ground reference voltage source 539 of FIG. 5 to deactivate the top select transistors 215 a and 215 c from their associated bit lines 225 a and 225 c and deactivate the bottom select transistors 220 a and 220 c from their associated bit lines 225 b and 225 d. To read the first charge trapping region 265 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b, the bit line controller 230 connects the second alternating bit line 225 c to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit lines 225 b. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 b that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 b to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and the value of the charge level of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and thus the value of the multiple digital data bits retained in the first charge trapping region 265 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b.

After the value of the multiple digital data bits is determined, the second charge trapping region 270 b of the selected dual-sided charge-trapping nonvolatile memory cell 205 b is then read. The bit line controller 230 connects the second alternating bit lines 225 b to the ground reference voltage 628 of FIG. 6 and activates the bit line drain voltage source 627 of FIG. 6 to transfer the read drain voltage (V_(DRAIN)) to the first alternating bit line 225 c. The word line controller 250 activates the read voltage source 546 to transfer the read voltage (V_(READ)) to the control gate of the selected dual-sided charge-trapping nonvolatile memory cells 205 a, 205 b, and 205 c that are turned on or not dependent upon the value of the read voltage (V_(READ)). Further, the word line controller 250 increments the voltage level of the read voltage (V_(READ)). The word line controller 230 senses the current through the selected dual-sided charge-trapping nonvolatile memory cells 205 b to determine the threshold of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and the value of the charge level in the second charge trapping regions 270 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b and thus the value of the multiple digital data bits retained in the second charge trapping regions 270 b of the selected dual-sided charge-trapping nonvolatile memory cells 205 b.

The erasure of the FIGS. 9 a and 9 b is as described for in FIG. 7 b where the erasure is shown as a row wise erase, where a selected row received a word line erase voltage level (V_(ERS)) from the selected word line 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−1, 235 m as applied by the word line controller 250. The word line erase voltage level is from approximately +15V to approximately +20V for n-channel dual-sided charge-trapping nonvolatile memory cells 205 to inject hot electrons into the charge trapping region. Alternately, if the dual-sided charge-trapping nonvolatile memory cells 205 are p-channel devices, the word line erase voltage level is from approximately −15V to approximately −20V to inject hot holes into the charge trapping region. The word line controller 250 applies the ground reference voltage level (0V) to the non-selected word lines 235 a, 235 b, . . . 235 j−1, 235 j, 235 j+1, . . . 235 m−, 235 m and thus to the dual-sided charge-trapping nonvolatile memory cells 205 to prevent removal of the trapped charges from the first and second charge trapping regions of the non-selected dual-sided charge-trapping nonvolatile memory cells 205.

The bit line controller 230 applies the ground reference voltage level (0V) to each of the associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n for a complete erase. In an array configuration, certain cells require that they not be subjected to the erasure operation. In this circumstance, the bit line controller 230 applies an inhibit voltage level (V_(INH)) of from approximately +7.5V to approximately +10V to those associated pair of bit lines 225 a, 225 b, 225 c, . . . 225 n−2, 225 n−1, 225 n that are sufficiently erased and do not require further erasure.

While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. 

1. A nonvolatile memory array comprising: a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns wherein said dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping of dual-sided charge-trapping nonvolatile memory cells that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor; a plurality of bit lines, connected such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines, such that a source/drain of said top select transistor is connected to a first of said associated pair of bit lines and a source/drain of said bottom select transistor is connected to a second of said associated pair of bit lines and such that said first of said associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and said second of said associated pair of bit lines is further associated with a second adjacent column of said dual-sided charge-trapping nonvolatile memory cells, wherein a source/drain of said top select transistor of said first adjacent column is connected to said second of said associated pair of bit lines and a source/drain of said bottom select transistor of said second adjacent column is connected to said first of said associated pair of bit lines; and a bit line controller connected to said plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.
 2. The nonvolatile memory array of claim 1 further comprising: a plurality of word lines, each word line associated with one row of said plurality of dual-sided charge-trapping nonvolatile memory cells; a plurality of top select lines, each top select line connected to a gate of said top select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; a plurality of bottom select lines, each bottom select line connected to a gate of said bottom select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and a word line controller connected to said word lines, said top select lines, and said bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing said trapped charges representing said multiple digital data bits within said charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.
 3. The nonvolatile memory array of claim 2 wherein said bit line controller comprises: a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits through said first of said associated pair of bit lines to said source/drain of said top select transistor to a first drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region; and a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region.
 4. The nonvolatile memory array of claim 2 wherein said word line controller comprises: a word line program voltage source that provides a very large program voltage for generating a voltage field between a control gate of said selected dual-sided charge-trapping nonvolatile memory cells and a channel region of said selected dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a charge trapping region of said selected dual-sided charge-trapping nonvolatile memory cell.
 5. The nonvolatile memory array of claim 2 wherein said word line controller comprises: a first select line program voltage source that selectively provides a moderately large select voltage to be transferred on said top select lines to activate said top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and a second select line program voltage source that selectively provides said moderately large select voltage to be transferred on said bottom select lines to activate said bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells.
 6. The nonvolatile memory array of claim 2 wherein: said word line controller comprises: a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of said selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of said plurality of threshold adjustment voltages representative of said portion of multiple digital data bits; and said bit line controller comprises: a read drain voltage generator that generates a drain voltage level that is selectively transferred through said first and second of said paired bit lines to said first drain/source and the second drain/source to activate said selected dual-sided charge-trapping nonvolatile memory cells dependent upon a trapped charge level within said charge trapping region; a first ground reference voltage generator to generate a ground reference voltage transferred selectively transferred through said first and second of said paired bit lines to said first and second drain/sources; and a sensing circuit connected through said pairs of bit lines to said selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of said charge trapping region representing said multiple digital data bits through said first and second of said paired bit lines.
 7. The nonvolatile memory array of claim 2 wherein: said word line controller comprises: a word line erase voltage source that provides a very large erase voltage for generating a voltage field between said channel region of said dual-sided charge-trapping nonvolatile memory cell and said control gate of said dual-sided charge-trapping nonvolatile memory cell to inject hot carriers to said charge trapping region to be extracted from the channel region of said dual-sided charge-trapping nonvolatile memory cell; and said bit line controller comprises: a second ground reference voltage generator to apply said ground reference voltage to said first and second drain/sources.
 8. The nonvolatile memory array of claim 4 wherein said dual-sided charge-trapping nonvolatile memory cell is an n-channel memory cell.
 9. The nonvolatile memory array of claim 8 wherein said very large program voltage has a level of from approximately −6.0V to approximately −10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.
 10. The nonvolatile memory array of claim 8 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.
 11. The nonvolatile memory array of claim 6 wherein said plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.
 12. The nonvolatile memory array of claim 11 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.
 13. The nonvolatile memory array of claim 7 wherein said very large erase voltage has voltage level of from approximately +15.0V to approximately +20V to increase said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.
 14. The nonvolatile memory array of claim 4 wherein said dual-sided charge-trapping nonvolatile memory cell is a p-channel memory cell.
 15. The nonvolatile memory array of claim 14 wherein said medium large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.
 16. The nonvolatile memory array of claim 14 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately −1.0V to approximately −6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.
 17. The nonvolatile memory array of claim 6 wherein said plurality of threshold detection voltages have a voltage range from approximately −2.0V to approximately −5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.
 18. The nonvolatile memory array of claim 17 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.
 19. The nonvolatile memory array of claim 14 wherein said very large erase voltage has voltage level of from approximately −15.0V to approximately −20V to decrease said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.
 20. A nonvolatile memory integrated circuit comprising: an array of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns wherein said dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping of dual-sided charge-trapping nonvolatile memory cells that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor; a plurality of bit lines, connected such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines, such that a source/drain of said top select transistor is connected to a first of said associated pair of bit lines and a source/drain of said bottom select transistor is connected to a second of said associated pair of bit lines and such that said first of said associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and said second of said associated pair of bit lines is further associated with a second adjacent column of said dual-sided charge-trapping nonvolatile memory cells, wherein a source/drain of said top select transistor of said first adjacent column is connected to said second of said associated pair of bit lines and a source/drain of said bottom select transistor of said second adjacent column is connected to said first of said associated pair of bit lines; a plurality of word lines, each word line connected to control gates of all said dual-sided charge-trapping nonvolatile memory cells of one of said rows of said array of said plurality dual-sided charge-trapping nonvolatile memory cells; a plurality of top select lines, each top select line connected to a gate of said top select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; a plurality of bottom select lines, each bottom select line connected to a gate of said bottom select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; a bit line controller connected to said plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells; and a word line controller connected to said word lines, said top select lines, and said bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing said trapped charges representing said multiple digital data bits within said charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.
 21. The nonvolatile memory integrated circuit of claim 20 wherein said word line controller comprises: a word line program voltage source that provides a very large program voltage for generating a voltage field between a control gate of said dual-sided charge-trapping nonvolatile memory cell and a channel region of said dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a charge trapping region of said dual-sided charge-trapping nonvolatile memory cell.
 22. The nonvolatile memory integrated circuit of claim 20 wherein said bit line controller comprises: a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits to a first drain/source of said nonvolatile memory cell array to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region; and a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said nonvolatile memory cell array to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region.
 23. The nonvolatile memory integrated circuit of claim 21 wherein said word line controller further comprises: a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of said selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of said plurality of threshold adjustment voltages representative of said portion of multiple digital data bits;
 24. The nonvolatile memory integrated circuit of claim 21 wherein said bit line controller further comprises: a read drain voltage generator that generates a drain voltage level that is selectively transferred through said first and second of said paired bit lines to first drain/source and the second drain/source to activate said selected dual-sided charge-trapping nonvolatile memory cell dependent upon a trapped charge level within said charge trapping region; a first ground reference voltage generator to generate a ground reference voltage transferred through said first and second of said paired bit lines to said first and second drain/sources; and a sensing circuit connected through said pairs of bit lines to said selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of said charge trapping region representing said multiple digital data bits through said first and second of said paired bit lines.
 25. The nonvolatile memory integrated circuit of claim 23 wherein said word line controller further comprises: a word line erase voltage source connected through said word lines to said selected dual-sided charge-trapping nonvolatile memory cells that provides a very large erase voltage for generating a voltage field between said channel region of said selected dual-sided charge-trapping nonvolatile memory cells and said control gate of said selected dual-sided charge-trapping nonvolatile memory cells to inject hot carriers to said charge trapping region to be extracted from the channel region of said selected dual-sided charge-trapping nonvolatile memory cells.
 26. The nonvolatile memory integrated circuit of claim 25 wherein said bit line controller comprises: a second ground reference voltage generator to apply said ground reference voltage to said first and second drain/sources.
 27. The nonvolatile memory integrated circuit 21 wherein each of said plurality dual-sided charge-trapping nonvolatile memory cells is an n-channel memory cell.
 28. The nonvolatile memory integrated circuit of claim 27 wherein said very large program voltage has a level of from approximately −6.0V to approximately −10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.
 29. The nonvolatile memory integrated circuit of claim 22 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.
 30. The nonvolatile memory integrated circuit of claim 23 wherein said plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.
 31. The nonvolatile memory integrated circuit of claim 30 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.
 32. The nonvolatile memory integrated circuit of claim 25 wherein said very large erase voltage has voltage level of from approximately +15.0V to approximately +20V to increase said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.
 33. The nonvolatile memory integrated circuit of claim 20 wherein each of said plurality dual-sided charge-trapping nonvolatile memory cells is a p-channel memory cell.
 34. The nonvolatile memory integrated circuit of claim 33 wherein said medium large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.
 35. The nonvolatile memory integrated circuit of claim 22 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately −1.0V to approximately −6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.
 36. The nonvolatile memory integrated circuit of claim 23 wherein said plurality of threshold detection voltages have a voltage range from approximately −2.0V to approximately −5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.
 37. The nonvolatile memory integrated circuit of claim 36 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.
 38. The nonvolatile memory integrated circuit of claim 25 wherein said very large erase voltage has voltage level of from approximately −15.0V to approximately −20V to decrease said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.
 39. A method for forming a nonvolatile memory array comprising the steps of: providing a plurality of dual-sided charge-trapping nonvolatile memory cells; arranging said plurality of dual-sided charge-trapping nonvolatile memory cells in rows and columns forming said dual-sided charge-trapping nonvolatile memory cells on each column into at least one grouping of dual-sided charge-trapping nonvolatile memory cells; arranging said connecting into a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor; connecting a plurality of bit lines, such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines, such that a source/drain of said top select transistor is connected to a first of said associated pair of bit lines and a source/drain of said bottom select transistor is connected to a second of said associated pair of bit lines and such that said first of said associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and said second of said associated pair of bit lines is further associated with a second adjacent column of said dual-sided charge-trapping nonvolatile memory cells, wherein a source/drain of said top select transistor of said first adjacent column is connected to said second of said associated pair of bit lines and a source/drain of said bottom select transistor of said second adjacent column is connected to said first of said associated pair of bit lines; and connecting a bit line controller to said plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.
 40. The method for forming said nonvolatile memory array of claim 39 further comprising the steps of: providing a plurality of word lines; connecting each word line with one row of said plurality of dual-sided charge-trapping nonvolatile memory cells; providing a plurality of top select lines; connecting each top select line to a gate of said top select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; providing a plurality of bottom select lines; connecting each bottom select line to a gate of said bottom select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and connecting a word line controller to said word lines, said top select lines, and said bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing said trapped charges representing said multiple digital data bits within said charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.
 41. The method for forming said nonvolatile memory array of claim 39 wherein said bit line controller comprises: a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits through said first of said associated pair of bit lines to said source/drain of said top select transistor to a first drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region; and a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region.
 42. The method for forming said nonvolatile memory array of claim 39 wherein said word line controller comprises: a word line program voltage source that provides a very large program voltage for generating a voltage field between a control gate of said selected dual-sided charge-trapping nonvolatile memory cells and a channel region of said selected dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a charge trapping region of said selected dual-sided charge-trapping nonvolatile memory cell.
 43. The method for forming said nonvolatile memory array of claim 39 wherein said word line controller comprises: a first select line program voltage source that selectively provides a moderately large select voltage to be transferred on said top select lines to activate said top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and a second select line program voltage source that selectively provides a moderately large select voltage to be transferred on said bottom select lines to activate said bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells.
 44. The method for forming said nonvolatile memory array of claim 39 wherein: said word line controller further comprises: a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of said selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of said plurality of threshold adjustment voltages representative of said portion of multiple digital data bits; and said bit line controller further comprises: a read drain voltage generator that generates a drain voltage level that is selectively transferred through said first and second of said paired bit lines to said first drain/source and the second drain/source to activate said selected dual-sided charge-trapping nonvolatile memory cells dependent upon a trapped charge level within said charge trapping region; a first ground reference voltage generator to generate a ground reference voltage transferred selectively transferred through said first and second of said paired bit lines to said first and second drain/sources; and a sensing circuit connected through said pairs of bit lines to said selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of said charge trapping region representing said multiple digital data bits through said first and second of said paired bit lines.
 45. The method for forming said nonvolatile memory array of claim 39 wherein: said word line controller further comprises: a word line erase voltage source that provides a very large erase voltage for generating a voltage field between said channel region of said dual-sided charge-trapping nonvolatile memory cell and said control gate of said dual-sided charge-trapping nonvolatile memory cell to inject hot carriers to said charge trapping region to be extracted from the channel region of said dual-sided charge-trapping nonvolatile memory cell; and said bit line controller further comprises: a second ground reference voltage generator to apply said ground reference voltage to said first and second drain/sources.
 46. The method for forming said nonvolatile memory array of claim 42 wherein said dual-sided charge-trapping nonvolatile memory cell is an n-channel memory cell.
 47. The method for forming said nonvolatile memory array of claim 46 wherein said very large program voltage has a level of from approximately −6.0V to approximately −10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.
 48. The method for forming said nonvolatile memory array of claim 46 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.
 49. The nonvolatile memory array of claim 44 wherein said plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.
 50. The method for forming said nonvolatile memory array of claim 49 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.
 51. The method for forming said nonvolatile memory array of claim 45 wherein said very large erase voltage has voltage level of from approximately +15.0V to approximately +20V to increase said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.
 52. The method for forming said nonvolatile memory array of claim 42 wherein said dual-sided charge-trapping nonvolatile memory cell is a p-channel memory cell.
 53. The method for forming said nonvolatile memory array of claim 52 wherein said very large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.
 54. The method for forming said nonvolatile memory array of claim 52 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately −1.0V to approximately −6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.
 55. The method for forming said nonvolatile memory array of claim 44 wherein said plurality of threshold detection voltages have a voltage range from approximately −2.0V to approximately −5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.
 56. The method for forming said nonvolatile memory array of claim 55 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.
 57. The method for forming said nonvolatile memory array of claim 52 wherein said very large erase voltage has voltage level of from approximately −15.0V to approximately −20V to decrease said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell. 